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Serial-in / Parallel-out Driver Series
Serial / Parallel 4-input Drivers
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
No.09051EAT03
Description Serial-in-parallel-out driver incorporates a built-in shift register and a latch circuit to control a maximum of 24 LED by a 4-line interface, linked to a microcontroller. A single external resistor can set the output current value of the constant current up to a maximum of 50mA. (BD7851FP only) CMOS open drain output type products can drive the maximum current of 25mA.
Features 1) LED can be driven directly. 2) Parallel output of a maximum of 24 bit 3) Operational on low voltage (2.7V to 5.5V) 4) Cascade connection is possible (BU2050F and BU2092F,BU2092FV are not acceptable)
Application For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment.
Product line-up Parameter Output current Output line Output type Package
BU2050F 25 8 CMOS SOP14
BU2092F 25 12
BU2092FV 25 12 Open drain
BU2099FV 25 12
BD7851FP 50 16 Constant current HSOP25
BU2152FS 25 24 CMOS SSOP-A32
Unit mA line -
SOP18
SSOP-B20
SSOP-B20
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1/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Thermal derating curve
700 Pd [mW] Pd [mW] 600 BU2050F 500 400 BU2099FV 300 200 100
85
Technical Note
700 600 BU2092F 500 400 300 200 100 0
Power dissipation
Power dissipation
BU2092FV
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
Ambient temperature Ta []
Ambient temperature Ta []
1600 Pd [mW] 1400 1200 1000 BU2152FS 800 600 400 200 0 25 50 75
85
BD7851FP
Power dissipation
100
125
150
175
Ambient temperature Ta []
Absolute maximum ratings (Ta=25) Parameter Power Supply Voltage Power dissipation 1 Power dissipation 2 Input Voltage Output Voltage Operating Temperature Storage Temperature
*1 Reduced by 4.5mW/ *2 Reduced by 4.5mW/ *3 Reduced by 4.0mW/ *4 Reduced by 5.5mW/ *5 Reduced by 6.5mW/
Symbol VDD Pd1 Pd2 VIN Vo Topr Tstg
BU2050F -0.3 to +7.0 450 *1 VSS-0.3 to VDD+0.5 VSS-0.3 to VDD+0.5 -40 to +85 -55 to +125
Limits BU2092F
BU2092FV
Unit V mW mW V V
-0.3 to +7.0 450 (SOP) *2 400 (SSOPB) *3 4 550 (SOP) * 650 (SSOPB) *5 VSS-0.3 to VDD+0.3 VSS to +25.0 -25 to +75 -55 to +125
over 25 over 25 over 25 for each increase in Ta of 1 over 25 (When mounted on a board 50mmx50mmx1.6mm Glass-epoxy PCB). for each increase in Ta of 1 over 25 (When mounted on a board 70mmx70mmx1.6mm Glass-epoxy PCB).
Parameter Power Supply Voltage Power dissipation 1 Power dissipation 2 Input Voltage Output Voltage Operating Temperature Storage Temperature
Symbol VDD Pd1 Pd2 VIN Vo Topr Tstg
BU2099FV -0.3 to +7.0 400 (SSOPB) *6 650 (SSOPB) *9 VSS-0.3 to VDD+0.3 VSS to +25.0 -40 to +85 -55 to +125
Limits BD7851FP 0 to +7.0 1450 *7 -0.3 to VCC+0.3 0 to +10 -30 to +85 -55 to +150
BU2152FS -0.3 to +7.0 800 *8 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 -25 to +85 -55 to +125
Unit V mW mW V V
*6 Reduced by 4.5mW/ over 25 *7 Reduced by 11.6mW/ over 25 *8 Reduced by 8.0mW/ over 25 *9 Reduced by 6.5mW/ for each increase in Ta of 1 over 25 (When mounted on a board 70mmx70mmx1.6mm Glass-epoxy PCB).
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2/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Electrical characteristics BU2050F (Unless otherwise noted, Ta=25, VDD=4.5 to 5.5V) Parameter Symbol Min. Power Supply Voltage VDD 4.5 Input high-level Voltage VIH 0.7VDD Input low-level Voltage VIL VSS Input Hysteresis VHYS VDD-1.5 Output high-level Voltage VOHD VDD-1.0 VDD-0.5 VSS Output low-level Voltage VOLD VSS VSS Quiescent Current IDD -
Technical Note
Typ. 0.5 -
Max. 5.5 VDD 0.3VDD VDD VDD VDD 1.5 0.8 0.4 0.1
Unit V V V V V
Condition
V mA
IOH=-25mA IOH=-15mA IOH=-10mA IOL=25mA IOL=15mA IOL=10mA VIH=VDD, VIL=VSS
BU2092F/BU2092FV (Unless otherwise noted, Ta=25, VSS=0V, VDD=5.0V/3.0V) Parameter Symbol Min. Typ. Max. Power Supply Voltage VDD 2.7 5.5 3.5 / 2.5 Input high-level Voltage VIH Input low-level Voltage VIL 1.5 / 0.4 Output low-level Voltage Output high-level disable Current Output low-level disable Current Quiescent Current VOL IOZH IOZL IDD 2.0 / 1.0 10.0 -5.0 5.0 / 3.0
Unit V V V V A A A
Condition VDD=5V/3V VDD=5V/3V VDD=5V/3V, IOL=20mA/5mA VO=25.0V VO=0V VIN=VSS or VDD (VDD=5V/3V) OUTPUT:OPEN
BU2099FV (Unless otherwise noted, Ta=25, VSS=0V, VDD=5.0V/3.0V) Parameter Symbol Min. Typ. Power Supply Voltage VDD 2.7 Input high-level Voltage VIH 3.5 / 2.1 Input low-level Voltage VIL VDD-0.5 Output high-level Voltage (SO) VOH / VDD-0.3 Output low-level Voltage 1 (Qx) VOL1 1.1 -
Max. 5.5 1.5 / 0.9 1.0 1.5 2.0 0.4 / 0.3 10 -5.0 150 / 60 2.4 200
Unit V V V V
Condition VDD=5V/3V VDD=5V/3V VDD=5V/3V, IOH=-400A/-100A VDD=5V/3V, IOL1=10mA/5mA VDD=5V, IOL1=15mA VDD=5V, IOL1=20mA VDD=5V/3V, IOL2=1.5mA/0.5mA VO=25.0V VO=0V OE= VDD, VDD=5V/3V VIN=VSS or VDD, VDD=5V OUTPUT:OPEN
V
Output low-level Voltage 2 (SO) Output high-level disable Current (Qx) Output low-level disable Current (Qx) IPULLDOWN (OE) Low Voltage Reset Quiescent Current
VOL2 IOZH IOZL IPD VCLR IDD
V A A A V A
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3/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Electrical characteristics BD7851FP (Unless otherwise noted, Ta=25, VCC=5.0V) Parameter Symbol Min. Power Supply Voltage VDD 4.5 0.8xVCC Input high-level Voltage VIH Input low-level Voltage Output high-level Voltage Output low-level Voltage VIL VOH VOL VCC-0.5 Quiescent Current ICC Reference Current Output Current (including the equation between each bit) Equation between each bit of Reference Current Output Current Change rate of reference current output current for output voltage Output Leak Current Iolc1 Iolc2 iolc IVCC IOH 48 5.0 4.0 30 55 5.9 1 1 0.01 6.5 40 62 6.8 6 6 0.8 mA mA mA mA % %/V A
Technical Note
Typ. 0.7 1.8
Max. 5.5 0.2xVCC 0.5 1.0 3.0
Unit V V V V V mA mA
Condition
IOH=-1mA IOL=1mA R=13k OUT1OUT16:OFF R=1.3k OUT1OUT16:OFF R=13k OUT1OUT16:ON R=1.3k OUT1OUT16:ON VOUT=2.0V, R=1.3k VOUT=2.0V, R=13k VOUTn=2.0V, R=1.3k (1bit : ON) VOUT=2.0 to 3.0V, R=1.3k VOUT=10V
BU2152FS (Unless otherwise noted, Ta=25, VDD=2.7 to 5.5V) Parameter Symbol Min. Typ. Power Supply Voltage VDD 2.7 2.0 Input high-level Voltage VIH Input low-level Voltage VIL VDD-1.5 Output high-level Voltage VOH VDD-1.0 VDD-0.5 Output low-level Voltage VOL Quiescent Current IDDST Input high-level Current IIH Input low-level Current IIL -
Max. 5.5 0.6 1.5 1.0 0.8 5 1 1
Unit V V V V
Condition VDD=5V VDD=5V IOH=-25mA IOH=-15mA IOH=-10mA IOL=25mA IOL=15mA IOL=10mA VIL=VSS, VIH=VDD
V A A A
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4/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Block diagram BU2050F STB CLR CLOCK DATA BU2092F/BU2092FV LCK CLOCK DATA Controller 12bit Shift Register L a t c h Controller Shift Register L a t c h
Technical Note
8bit
Write Buffer P1P8
Write Buffer Q0Q11
OE BU2099FV LCK CLOCK DATA LPF Controller 12bit Shift Register L a t c h
Write Buffer Q0Q11
OE BD7851FP S_IN Shift CLOCK Register L a t c h
16bit
Write Buffer OUT1OUT16
LATCH ENABLE R_Iref Current Adjustment
SOUT
BU2152FS STB CLB CLOCK DATA Controller Shift Register
24bit
L a t c h
Write Buffer P1P24 SO
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5/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
Operating description (1) Data clear When the reset terminal (CLR, CLB) is set to "L", the content of all latch circuits are set to "H", and all parallel outputs are initialised. (For model with reset terminal only) (2) Data transfer Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When the strobe signal is active, the content of the shift register are transferred to the latch circuit. (3) Cascade connection Serial input data is output from the serial output through the shift register, regardless of the strobe signal. (except for BU2050F, BU2092F/BU2092FV) Application circuit
C1 (*) VDD
P1 P2 VDD Serial data input Clock input Strobe input Latch input
Pn-2 Pn-1 Pn
MPU
VSS
VSS Serial data output
P1 P2 VDD Serial data input Clock input Strobe input Latch input
Pn-2 Pn-1 Pn
VSS Serial data output (*C1 must be placed as close to the terminal as possible.)
Fig. 1 BU2092F/BU2092FV Q0Q11
OUT
Interfaces BU2050F DATA, CLOCK, STB, CLR
VDD VDD
BU2050F P1P8
BU2092F/BU2092FV DATA, CLOCK, LCK, OE
VDD VDD
INPUT
OUTPUT
IN
GND(VSS) GND(VSS) GND(VSS) GND(VSS) GND(VSS) GND(VSS) GND(VSS)
BU2099FV DATA, CLOCK, LCK, OE
VDD VDD VDD
BU2099FV Q0Q11
OUT
BU2099FV SO
VDD
BU2152FS CLOCK, DATA, STB, CLB
VDD VDD VDD
IN
OUT
(only OE pin) GND(VSS) GND(VSS) GND(VSS)
GND(VSS) GND(VSS) GND(VSS) GND(VSS) GND(VSS)
BU2152FS P1P28
VDD VDD VDD
BU2152FS SO
VDD VDD
VSS
VSS
VSS
GND(VSS)
GND(VSS) GND(VSS)
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6/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2050F Pin descriptions Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 P3 P4 P5 VSS P6 P7 P8 DATA CLK STB Serial Data Input Parallel Data Output GND Parallel Data Output
Technical Note
Function
11 12 13 14 Timing chart
CLK
CLR P1 P2 VDD
Clock Signal Input Strobe Signal Input In case of "L", the data of shift register outputs. In case of "H", all parallel outputs and data of latch circuit do not change. Reset Signal Input In case of "L", the data of latch circuit reset, and all parallel output (P1P8) can be L. Normally CLR=H Parallel Data output Power Supply
DATA
DATA8
DATA7
DATA6
DATA2
DATA1
CLR
STB
Pn
Previous DATA
DATA
"L"
Fig. 2 1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the DATA pin. th 2. Pn parallel output data of the shift register is set after the 8 clock by the STB. 3. Since the STB is level latch, data is retained in the "L" section and renewed in the "H" section of the STB. Function explanation A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is "L", the latch circuit is reset non-synchronously without the other input condition, and all parallel output can be "L". A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock. In case of STB is "L" (CLR is "H"), transmit the data which read in the shift register to latch circuit, and outputs from the parallel data output terminal (P1P8). In case of STB is "H", all parallel outputs and the data of latch do not change.
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7/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Switching characteristics (Unless otherwise specified, VDD=4.5 to 5.5V, Ta=25) Limit Parameter Symbol Unit Min. Typ. Max. Set up time (DATA-CLK) Hold time (DATA-CLK) Set up time ( STB CLK) Hold time ( STB CLK) Propagation ( CLR P1P8) Propagation ( STB P1P8) Propagation ( CLR P1P8) Maximum clock frequency tSD tHD tSSTB tHSTB tPDPCK tPDPSTB tPDPCLR fMAX 20 20 30 30 5 100 80 80 ns ns ns ns ns ns ns MHz
Technical Note
Condition P1P8 terminal load 20pF or less P1P8 terminal load 20pF or less P1P8 terminal load 20pF or less -
Switching Time Test Waveform
fMAX
1 CLK
tSD
2
8
9
10
11
12
DATA STB
tHD
tHSTB
tSSTB
CLR
P8
P1
tPDPSTB
tPDPCLR
Fig. 3
tPDPCK
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8/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2092F/BU2092FV Pin descriptions Pin No. 1 2 3 4 511, 1418 12, 13 17 18 Timing chart
CLOCK
Technical Note
Pin Name VSS DATA CLOCK LCK
I/O I I I
Function GND Serial Data Input Shift clock of DATA (Rising Edge Trigger) Latch clock of DATA (Rising Edge Trigger) Parallel Data Output (Nch Open Drain FET) Latch Data L H Output FET ON OFF
Q0Q11
O
N.C. OE VDD
I -
Non connected Output Enable ("H" level : output FET is OFF) Power Supply
DATA
DATA11
DATA10
DATA9
DATA1
DATA0
LCK
OE
Qx
"H"
Previous DATA
DATA110 Note) Diagram shows a status where a pull-up resistor is connected to output.
Fig. 4 1. 2. 3. 4. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into the DATA terminal. th Qx parallel output data of the shift register is set after the 12 clock by the LCK. Since the LCK is a label latch, data is retained in the "L" section and renewed in the "H" section of the LCK. Data retained in the internal latch circuit is output when the OE is in the "L" section.
Truth Table Input CLOCK x x DATA x x L H x x x LCK x x x x x OE H L x x x x x Function Output (Q0Q11) Disable Output (Q0Q11) Enable Store "L" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) Store "H" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) The data of shift register has no change. The data of shift register is transferred to the storage register. The data of storage register has no change.
x x
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9/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25) Parameter Symbol Limit Min. 1000 500 1000 500 400 200 400 200 400 200 Typ. 90 55 115 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Technical Note
VDD(V) 3 5 3 5 3 5 3 5 3 5 3 5 3 5
Condition
Minimum Clock Pulse Width Minimum Latch Pulse Width (LCK) Setup Time (LCKCLOCK) Setup Time (DATACLOCK) Hold Time (CLOCKDATA)
tw tw (LCK) ts
-
-
-
tsu
-
tH tPLZ (LCK) tPZL (LCK)
RL=5k CL=10pF RL=5k CL=10pF
Propagation (LCKOUTPUT QX)
Propagation ( OE OUTPUT QX)
tPLZ
-
70 45 80 35
-
ns ns ns ns
3 5 3 5
RL=5k CL=10pF RL=5k CL=10pF
tPZL
Switching Time Test Circuit
VDD
Pulse Gen.
25V RL Q0 CL GND (Vss)
CLOCK
Pulse Gen.
LCK
Pulse Gen.
25V DATA RL OE Q11 CL GND (Vss) GND (Vss)
Pulse Gen.
Fig. 5
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10/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2092F/BU2092FV Switching Time Test Waveforms
tW
90% 90% 90%
Technical Note
tW
90%
VDD
CLOCK
10%
10%
10%
GND (VSS)
tSU
tH VDD tS GND (VSS)
90%
90%
DATA
tW(CLK)
90% 90%
VDD
LCK
50% 10%
50%
GND (VSS)
tPLZ(LCK)
tPZL(LCK)
50% 50%
VDD
OE
tPLZ
50% 10%
GND (VSS) tPZL VDD
50%
Qx
10%
GND (VSS)
Fig. 6
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11/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2099FV Pin descriptions
Technical Note
Pin No. 1 2 3 4 5
Pin Name VSS N.C. DATA CLOCK LCK Q0Q11 (Qx) SO OE VDD
I/O I I I
Function GND Non connected Serial Data Input Shift clock of Shift register (Rising Edge Trigger) Latch clock of Storage register (Rising Edge Trigger) Parallel Data Output (Nch Open Drain FET) Latch Data L H Output FET ON OFF Serial Data Output Output Enable Control Input Power Supply
617
O
18 19 20
Timing chart
CLOCK
O I -
OE pin is pulled down to Vss.
DATA
DATA12
DATA11
DATA10
DATA2
DATA1
LCK
OE Qx
"H" Previous DATA DATA
SO
Previous DATA 11
Previous DATA 11
DATA12
DATA11
Fig. 7 1. 2. 3. 4. 5. After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into the DATA terminal. Qx parallel output data of the shift register is set after the 12th clock by the LCK. Since the LCK is a label latch, data is retained in the "L" section and renewed in the "H" section of the LCK. Data retained in the internal latch circuit is output when the OE is in the "L" section. The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
Truth Table
Input CLOCK x x
DATA x x L H x
LCK x x x x x
OE H L x x x x x
Function All the output data output "H" with pull-up. The Q0Q11 output can be enable and output the data of storage register. Store "L" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) Store "H" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) The data of shift register has no change. SO outputs the final stage data of shift register with synchronized falling edge of CLOCK, not controlled by OE. The data of shift register is transferred to the storage register. The data of storage register has no change.
x x
x x
The Q0Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is "L", and Tr is OFF when data is "H".
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12/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2099FV Switching characteristics
Technical Note
(Unless otherwise specified, VDD=5V, VSS=0V, Ta=25) Limit Parameter Symbol Unit Min. Typ. Max. 1000 ns Minimum Clock Pulse Width tW (CLOCK) 500 ns 1000 ns Minimum Latch Pulse Width tW (LCK) (LCK) 500 ns 400 ns Setup Time tS (LCKCLOCK) 200 ns 400 ns Setup Time tsu (DATACLOCK) 200 ns 400 ns Hole Time tH (CLOCKDATA) 200 ns 500 ns Propagation tPLH (SO) tPHL 250 ns 360 ns tPLZ (LCK) Propagation 170 ns (LCKQX) * 260 ns tPZL (LCK) 175 ns 115 ns tPLZ Propagation 85 ns ( QE QX) * 175 ns tPZL 65 ns 30 ns Noise Pulse Suppression tI Time (LCK) * 20 ns
VDD(V) 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 -
Condition RL=5k CL=10pF RL=5k CL=10pF RL=5k CL=10pF RL=5k CL=10pF -
*Reference value
Input Voltage Test Circuit
RL =10k
GND (Vss) P.G. VIH VIL GND
Fig. 8
+25V RL =5k CL =10pF GND (Vss)
Switching Time Test Circuit
VDD
GND (Vss) P.G.
+25V RL =5k CL =10pF GND (Vss)
Fig. 9
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13/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2099FV Output Voltage Test Circuit
VDD
Technical Note
25V 12 SW3 1 SW2 3 2 GND (Vss) P.G. 1 SW1 IOL1 IOH IOL2 1 SW4 2
GND (Vss)
GND (Vss)
GND (Vss)
GND (Vss)
GND (Vss)
GND (Vss)
Test condition VOL1 Set all data "L". SW1="ON", SW2="3", SW3="1""12". VOL2 Set output data "L" to SO and SW4 is positioned to "2", then voltage is measured at IOL2. VOH Set output data "H" to SO and SW4 is positioned to "1", then voltage is measured at IOH.
Fig. 10
Switching Time Test Waveforms
tW
90% 50% 90% 90%
tW
90% 50% 50%
VDD
CLOCK
10%
10%
10%
GND (VSS)
tSU
90%
tH
90%
VDD tS GND (VSS) tW (CLK)
90% 90%
DATA
VDD
LCK
50%
50%
tS 2 tPLZ(LCK)
10%
tPLZ
GND (VSS) VDD
50% 50%
OE
tPZL(LCK) tPZL
GND (VSS)
VEXT
Qx
50% 10% 10%
50%
tPLH
tPHL
GND (VSS)
VDD
50% 50%
SO
GND (VSS)
Fig. 11
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14/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BD7851FP Pin descriptions
Technical Note
Pin No. 1 2 3 4 515 16 1721 22 23 24 25
Timing chart
CLOCK
Pin Name GND R_Iref LATCH S_IN OUT16 OUT6 P_GND OUT5 OUT1 SOUT CLOCK ENABLE VCC
Function Ground Reference Current Output Current setting Latch Signal Input Serial Data Input Reference Current Output Ground for Driver Reference Current Output Serial Data Output Clock Input ENABLE VCC
S_IN LATCH
DATA16
DATA15
DATA14
DATA2
DATA1
ENABLE
OUTn
Previous DATA15
Previous DATA
DATA
SOUT
Previous DATA14
Previous DATA2
Previous DATA1
DATA16
DATA15
DATA14
Fig. 12 1. 2. 3. 4. 5. After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits into the S_IN terminal. OUTn parallel output data of the shift register is set after the 16th clock by the LATCH. The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the CLOCK. Since the LATCH is a label latch, data is retained in the "L" section and renewed in the "H" section of the LATCH. Data retained in the internal latch circuit is outputted when the ENABLE is in the "L" section. When the ENABLE is in the "H" section, data is fixed in the "H" section.
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15/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BD7851FP Timing characteristics
Technical Note
(Unless otherwise specified, VCC=5V, Ta=25) Limit Parameter Symbol Min. Typ. Max. Frequency CLOCK fclk 10 Pulse Width CLOCK twh 20 50 Pulse Width LATCH twh 40 50 Pulse Width ENABLE tw 30 Rise Time / Fall Time tr / tf 30 100 30 50 Setup Time tSU 30 50 30 50 Hold Time th 30 50 300 Rise Time tr 50 300 Fall Time tf 50
Unit MHz ns ns ns ns ns ns ns ns
Condition
tpLH Propagation tpHL
Reference Current of Output Current
250
-
400 300
650 ns 400
CLOCK LATCH ENABLE CLOCK S_IN-CLOCK LATCH-CLOCK S_IN-CLOCK LATCH-CLOCK OUTn SOUT OUTn SOUT CLK-SOUT, LATCH ENABLE-OUTn CLK-SOUT, LATCH ENABLE-OUTn
[Condition] Vcc=5.0V, Vo=5.0V, Ta=25
The reference current of output current is determined by the external resistor. (between 2pin and GND )
200
IOUT [mA]
150
100
50
0 0.1 1 R_Iref [k] 10 100
This is a data for the standard sample, not guaranteed the characteristic.
Fig. 13
R_Iref-VOUT
1.6 1.4 1.2 1.0
VOUT [V]
[Condition] Vcc=5.0V, Ta=27, all bit : ON
0.8 0.6 0.4 0.2 0.0 1 10 R_Iref [k] 100
Notes the increase of consumption current Icc, in case sets the voltage of VOUT lower. See the graph above.
Fig. 14
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16/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BD7851FP Test Circuit 1
Vcc R
Technical Note
1 GND 2 R_Iref
Vcc 25 ENABLE 24 CLOCK 23 SOUT 22 OUT1 21 OUT2 20
VE ENABLE CLOCK SOUT
LATCH S_IN
3 LATCH 4 S_IN 5 OUT16 6 OUT15
BD7851FP
7 OUT14 8 OUT13 9 OUT12 10 OUT11 11 OUT10 12 OUT9 13 OUT8
OUT3 19 OUT4 18 OUT5 17 P_GND 16 OUT6 15 OUT7 14
P_GND
Fig. 15
Test Circuit 2
Vcc R
1 GND 2 R_Iref
Vcc 25 ENABLE 24 CLOCK 23 SOUT 22 OUT1 21 OUT2 20
VE ENABLE CLOCK SOUT
LATCH S_IN
3 LATCH 4 S_IN 5 OUT16 6 OUT15
BD7851FP
7 OUT14 8 OUT13 9 OUT12 10 OUT11 11 OUT10 12 OUT9 13 OUT8
OUT3 19 OUT4 18 OUT5 17 P_GND 16 OUT6 15 OUT7 14
P_GND
R=51 (note : R_Iref=1.3k) , C=15pF
Fig. 16
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17/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BD7851FP Switching Time Test Waveforms
tr tWh
0.8xVCC 0.8xVCC
Technical Note
tf
0.8xVCC
CLOCK
0.2xVCC
0.2xVCC
tSU
0.8xVCC
th
0.8xVCC
S_IN
twh
0.8xVCC
LATCH
th
0.2xVCC
tSU
tpHL
90% 90%
tpHL
90% 10%
OUTn
tpHLtpLH
10%
10%
tf
tr
0.8xVCC
ENABLE
tw
0.2xVCC
0.8xVCC
SOUT
tpHLtpLH tftr
0.2xVCC
Fig. 17
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18/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2152FS Pin descriptions Pin Pin Name No.
Technical Note
I/O I I O O I I -
Function Ground Clock Input Ground Serial Data Input Parallel Data Output Cascade Output Strobe Signal Input active "L" Clear Signal Input active "L" Power Supply
1 2 3 4 528 29 30 31 32
Timing chart
CLK
VSS CLK VSS DATA P1P24 SO STB CLB VDD
DATA
DATA24
DATA23
DATA22
DATA2
DATA1
STB
Pn
Previous DATA
DATA
SO
Previous DATA24
Previous DATA23
Previous DATA2
Previous DATA1
DATA24
DATA23
DATA22
Fig. 18 1. 2. 3. 4. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits into the DATA terminal. Pn parallel output data of the shift register is set after the 24th clock by the LCK. Since the STB is a label latch, data is retained in the "H" section and renewed in the "L" section of the STB. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLOCK.
Truth Table
CLK x
Input STB x H
CLB L H
Function All the data of the latch circuit are set to "H" (data of shift register does not change), all the parallel outputs are "H". Serial data of DATA pin are latched to the shift register. At this time, the data of the latch circuit does not change. The data of the shift register are transferred to the latch circuit, and the data of the latch circuit are outputted from the parallel output pin. The data of the shift register shifts 1bit, and the data of the latch circuit and parallel output also change.
L H
L
H
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19/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
BU2152FS Switching characteristics
Technical Note
(Unless otherwise specified, VDD=2.7 to 5.5V, VSS=0V, Ta=25)
Parameter Maximum Clock Frequency Setup Time 1 Hold Time 1 Setup Time 2 Hold Time 2 Setup Time 3 Hold Time 3 Setup Time 4 Hold Time 4 Output Delay Time 1* Output Delay Time 2* Output Delay Time 3*
*50pF of load is attached.
Symbol fMAX tSU1 tHD1 tSU2 tHD2 tSU3 tHD3 tSU4 tHD4 tPD1 tPD2 tPD3.
Limit Min. 5 20 20 30 30 30 30 30 30 Typ. Max. 100 80 80
Unit MHz ns ns ns ns ns ns ns ns ns ns ns
Condition
DATA-CLK CLK-DATA STB-CLK CLK-STB CLB-CLK CLK-CLB STB-CLB CLB-STB CLK-P1P24 STB-P1P24 CLB-P1P24
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20/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Switching characteristic conditions Setup/Hold Time (DATA-CLOCK, STB-CLOCK, CLB-CLOCK)
tr tr
Technical Note
90%
90% 50% 10%
CLOCK DATA
50% 10%
tSU1
tHD1
STB
50% 50%
tHD2
tSU2
CLB
50% 50%
Setup/Hold Time (STB-CLB)
CLB
tHD3
50%
tSU3
STB
tSU4 tHD4
Fig. 19 Switching characteristic conditions 1
Output Delay Time (CLOCK-P1P24)
CLOCK
50%
tPD1
P1P24
Output Delay Time (STB-P1P24)
STB
50%
tPD2
P1P24
Output Delay Time (CLB-P1P24)
CLB
50%
tPD3
50%
Fig. 20 Switching characteristic conditions 2
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21/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Notes for use
Technical Note
1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 10. Unused input terminals Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation. Insertion of a resistor (100k approx.) is also recommended.
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22/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Ordering part number
Technical Note
B
U
2
Part No. 2050 2092 2099 7851 2152
0
9
2
F
V
-
E
2
Part No.
Package F : SOP14 : SOP18 FV : SSOP-B20 FP : HSOP25 FS : SSOP-A32
Packaging and forming specification E2: Embossed tape and reel
SOP14

8.7 0.2 (MAX 9.05 include BURR)
14 8
Tape Quantity Direction of feed
0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.20.3
4.40.2
( reel on the left hand and you pull out the tape on the right hand
)
1
7
0.15 0.1
1.50.1
0.11
1.27
0.4 0.1
0.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SOP18

11.2 0.2 (MAX 11.55 include BURR)
18 10
Tape Quantity Direction of feed
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
7.80.3
5.40.2
1
9
0.15 0.1
1.80.1
0.11
0.1 1.27 0.4 0.1
0.3MIN
( reel on the left hand and you pull out the tape on the right hand
)
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SSOP-B20
6.5 0.2
20 11

Tape Quantity
0.3Min.
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.4 0.3
4.4 0.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1
10
0.15 0.1
1.15 0.1
0.1 0.1
0.1 0.65 0.22 0.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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23/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
HSOP25

13.6 0.2
(MAX 13.95 include BURR)
Tape Quantity
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
2.75 0.1
25 14
7.8 0.3
5.4 0.2
1
13
1.95 0.1
1.9 0.1
0.25 0.1 S
0.11
0.8 0.36 0.1 12.0 0.2
0.1 S
0.3Min.
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
SSOP-A32

13.6 0.2 (MAX 13.95 include BURR)
32 17
Tape Quantity Direction of feed
0.3MIN
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
7.80.3
5.40.2
( reel on the left hand and you pull out the tape on the right hand
)
1
16
1.80.1
0.15 0.1
0.11
0.36 0.1 0.8
0.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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24/24
2009.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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